diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cache.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cache.kt index 75785ca..d87c9ca 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cache.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cache.kt @@ -7,36 +7,43 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `struct cpuinfo_cache` + * CPU缓存结构体 */ data class Cache( /** * Cache size in bytes + * 缓存大小（字节） */ val size: UInt, /** * Number of ways of associativity + * 缓存关联路数 */ val associativity: UInt, /** * Number of sets + * 缓存组数 */ val sets: UInt, /** * Number of partitions + * 分区数量 */ val partitions: UInt, /** * Line size in bytes + * 缓存行大小（字节） */ val lineSize: UInt, /** * Binary characteristics of the cache (unified cache, inclusive cache, * cache with complex indexing). + * 缓存的二进制特性标志（统一缓存、包容缓存、复杂索引缓存） * * @see `CPUINFO_CACHE_UNIFIED`, `CPUINFO_CACHE_INCLUSIVE`, * `CPUINFO_CACHE_COMPLEX_INDEXING` @@ -45,11 +52,13 @@ data class Cache( /** * Index of the first logical processor that shares this cache + * 共享此缓存的第一个逻辑处理器的索引 */ val processorStart: UInt, /** * Number of logical processors that share this cache + * 共享此缓存的逻辑处理器数量 */ val processorCount: UInt, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cluster.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cluster.kt index 3760ee5..7bf279d 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cluster.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Cluster.kt @@ -7,64 +7,78 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `struct cpuinfo_cluster` + * CPU核心集群信息结构体（big.LITTLE架构中的大核小核集群） */ data class Cluster( /** * Index of the first logical processor in the cluster + * 集群中第一个逻辑处理器的索引 */ val processorStart: UInt, /** * Number of logical processors in the cluster + * 集群中的逻辑处理器数量 */ val processorCount: UInt, /** * Index of the first core in the cluster + * 集群中第一个核心的索引 */ val coreStart: UInt, /** * Number of cores on the cluster + * 集群中的核心数量 */ val coreCount: UInt, /** * Cluster ID within a package + * 封装内的集群ID */ val clusterId: UInt, /** * Physical package containing the cluster + * 包含此集群的物理封装 */ val cpuPackage: Package, /** * CPU microarchitecture vendor of the cores in the cluster + * 集群中核心的CPU微架构供应商 */ val vendor: Vendor, /** * CPU microarchitecture of the cores in the cluster + * 集群中核心的CPU微架构 */ val uarch: Uarch, /** * x86 only + * 仅x86架构 * * Value of CPUID leaf 1 EAX register of the cores in the cluster + * 集群中核心的CPUID leaf 1 EAX寄存器值 */ val cpuid: UInt?, /** * ARM and ARM64 only + * 仅ARM和ARM64架构 * * Value of Main ID Register (MIDR) of the cores in the cluster + * 集群中核心的主ID寄存器（MIDR）值 */ val midr: Midr?, /** * Clock rate (non-Turbo) of the cores in the cluster, in Hz + * 集群中核心的时钟频率（非睿频），单位赫兹（Hz） */ val frequency: ULong, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Core.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Core.kt index 6e1fe9a..e728217 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Core.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Core.kt @@ -7,59 +7,72 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `struct cpuinfo_core` + * CPU核心信息结构体 */ data class Core( /** * Index of the first logical processor on this core. + * 此核心上第一个逻辑处理器的索引 */ val processorStart: UInt, /** * Number of logical processors on this core + * 此核心上的逻辑处理器数量 */ val processorCount: UInt, /** * Core ID within a package + * 核心在封装内的ID */ val coreId: UInt, /** * Cluster containing this core + * 包含此核心的集群 */ val cluster: Cluster, /** * Physical package containing this core. + * 包含此核心的物理封装 */ val cpuPackage: Package, /** * Vendor of the CPU microarchitecture for this core + * 此核心的CPU微架构供应商 */ val vendor: Vendor, /** * CPU microarchitecture for this core + * 此核心的CPU微架构 */ val uarch: Uarch, /** * x86 only + * 仅x86架构 * * Value of CPUID leaf 1 EAX register for this core + * 此核心的CPUID leaf 1 EAX寄存器值 */ val cpuid: UInt?, /** * ARM and ARM64 only + * 仅ARM和ARM64架构 * * Value of Main ID Register (MIDR) for this core + * 此核心的主ID寄存器（MIDR）值 */ val midr: Midr?, /** * Clock rate (non-Turbo) of the core, in Hz + * 核心的时钟频率（非睿频），单位赫兹（Hz） */ val frequency: ULong, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/LinuxCpu.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/LinuxCpu.kt index f302d02..6f3aae6 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/LinuxCpu.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/LinuxCpu.kt @@ -9,7 +9,15 @@ import okio.FileSystem import okio.Path import okio.Path.Companion.toPath +/** + * Linux CPU information from sysfs + * 从sysfs获取的Linux CPU信息 + */ data class LinuxCpu( + /** + * CPU ID (0-based) + * CPU编号（从0开始） + */ val id: Int, ) { private val cpuBaseDir = CPUINFO_BASE_DIR / "cpu${id}" @@ -18,55 +26,78 @@ data class LinuxCpu( require(FILESYSTEM.exists(cpuBaseDir)) { "CPU $id doesn't exist" } } + /** + * Whether this CPU is online + * 此CPU是否在线 + */ val isOnline: Boolean? get() = getIntArray(ONLINE_CPUS)?.contains(id) /** * Current frequency, in Hz. + * 当前频率，单位赫兹（Hz） */ val currentFrequencyHz: Long? get() = getLong(cpuBaseDir / CPUINFO_CURRENT_FREQ)?.let { it * 1000 } /** * Minimum frequency, in Hz. + * 最小频率，单位赫兹（Hz） */ val minimumFrequencyHz: Long? get() = getLong(cpuBaseDir / CPUINFO_MINIMUM_FREQ)?.let { it * 1000 } /** * Maximum frequency, in Hz. + * 最大频率，单位赫兹（Hz） */ val maximumFrequencyHz: Long? get() = getLong(cpuBaseDir / CPUINFO_MAXIMUM_FREQ)?.let { it * 1000 } /** * Current frequency, in Hz. + * 当前频率（调频器），单位赫兹（Hz） */ val scalingCurrentFrequencyHz: Long? get() = getLong(cpuBaseDir / SCALING_CURRENT_FREQ)?.let { it * 1000 } /** * Minimum frequency, in Hz. + * 最小频率（调频器），单位赫兹（Hz） */ val scalingMinimumFrequencyHz: Long? get() = getLong(cpuBaseDir / SCALING_MINIMUM_FREQ)?.let { it * 1000 } /** * Maximum frequency, in Hz. + * 最大频率（调频器），单位赫兹（Hz） */ val scalingMaximumFrequencyHz: Long? get() = getLong(cpuBaseDir / SCALING_MAXIMUM_FREQ)?.let { it * 1000 } // File utils + // 文件工具方法 + /** + * Read a string from a sysfs file + * 从sysfs文件读取字符串 + */ private fun getString(path: Path) = runCatching { FILESYSTEM.read(path) { readUtf8Line() } }.getOrNull() + /** + * Read a long value from a sysfs file + * 从sysfs文件读取长整型值 + */ private fun getLong(path: Path) = getString(path)?.toLongOrNull() + /** + * Parse CPU list from sysfs (e.g., "0-3,5,7-9" -> [0,1,2,3,5,7,8,9]) + * 从sysfs解析CPU列表（例如，"0-3,5,7-9" -> [0,1,2,3,5,7,8,9]） + */ private fun getIntArray(path: Path) = getString(path)?.let { mutableListOf().apply { for (item in it.split(",")) { @@ -85,6 +116,10 @@ data class LinuxCpu( } companion object { + /** + * Base directory for CPU information in sysfs + * sysfs中CPU信息的基础目录 + */ val CPUINFO_BASE_DIR = "/sys/devices/system/cpu".toPath() private val FILESYSTEM = FileSystem.SYSTEM @@ -99,6 +134,10 @@ data class LinuxCpu( private const val SCALING_MINIMUM_FREQ = "cpufreq/scaling_min_freq" private const val SCALING_MAXIMUM_FREQ = "cpufreq/scaling_max_freq" + /** + * Create LinuxCpu from Processor + * 从Processor创建LinuxCpu + */ fun fromProcessor(processor: Processor) = LinuxCpu(processor.linuxId.toInt()) } } diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Midr.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Midr.kt index 030712a..e8ef06a 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Midr.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Midr.kt @@ -7,33 +7,117 @@ package com.xyzshell.andinfo.libs.cpu.models /** * ARM and ARM64 only + * 仅ARM和ARM64架构 * * B4.1.105 MIDR, Main ID Register, VMSA + * 主ID寄存器（MIDR），用于识别ARM处理器 */ data class Midr( + /** + * ARM processor implementer + * ARM处理器实现者/制造商 + */ val implementer: Implementer, + + /** + * Variant number + * 变体号 + */ val variant: UByte, + + /** + * Architecture version + * 架构版本 + */ val architecture: Architecture, + + /** + * Primary part number + * 主要部件编号 + */ val primaryPartNumber: UInt, + + /** + * Revision number + * 修订号 + */ val revision: UByte, ) { + /** + * ARM processor implementer codes + * ARM处理器实现者代码 + */ enum class Implementer(val value: UByte) { + /** + * Unknown implementer + * 未知实现者 + */ UNKNOWN(0x00U), // From ARM spec + // 来自ARM规范 + /** + * ARM Holdings + * ARM控股公司 + */ ARM(0x41U), + /** + * Digital Equipment Corporation + * 迪吉多公司 + */ DEC(0x44U), + /** + * Motorola/Freescale + * 摩托罗拉/飞思卡尔 + */ MOTOROLA(0x4DU), + /** + * Qualcomm + * 高通 + */ QUALCOMM(0x51U), + /** + * Marvell + * 美满电子 + */ MARVELL(0x56U), + /** + * Intel + * 英特尔 + */ INTEL(0x69U), // Implementers not declared in the spec, taken from cpuinfo's arm/uarch.c + // 规范中未声明的实现者，取自cpuinfo的arm/uarch.c + /** + * Broadcom + * 博通 + */ BROADCOM(0x42U), + /** + * Cavium + * Cavium公司 + */ CAVIUM(0x43U), + /** + * Huawei (HiSilicon) + * 华为（海思） + */ HUAWEI(0x48U), + /** + * Nvidia + * 英伟达 + */ NVIDIA(0x4EU), + /** + * Applied Micro + * 应用微电路 + */ APM(0x50U), + /** + * Samsung + * 三星 + */ SAMSUNG(0x53U); companion object { @@ -41,6 +125,10 @@ data class Midr( } } + /** + * ARM architecture versions + * ARM架构版本 + */ enum class Architecture(val value: UByte) { ARMV4(0x1U), ARMV4T(0x2U), @@ -49,6 +137,10 @@ data class Midr( ARMV5TE(0x5U), ARMV5TEJ(0x6U), ARMV6(0x7U), + /** + * Defined by CPUID register + * 由CPUID寄存器定义 + */ DEFINED_BY_CPUID(0xFU); companion object { @@ -57,6 +149,10 @@ data class Midr( } companion object { + /** + * Parse MIDR value from cpuinfo + * 从cpuinfo解析MIDR值 + */ fun fromCpuInfo(value: Int) = Midr( Implementer.fromValue(value.shr(24).and(0xFF).toUByte()), value.shr(20).and(0xF).toUByte(), diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Package.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Package.kt index 4d3e45a..e738479 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Package.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Package.kt @@ -5,39 +5,49 @@ package com.xyzshell.andinfo.libs.cpu.models +/** + * CPU物理封装信息 + */ data class Package( /** * SoC or processor chip model name + * SoC或处理器芯片型号名称 */ val name: String, /** * Index of the first logical processor on this physical package + * 此物理封装上第一个逻辑处理器的索引 */ val processorStart: UInt, /** * Number of logical processors on this physical package + * 此物理封装上的逻辑处理器数量 */ val processorCount: UInt, /** * Index of the first core on this physical package + * 此物理封装上第一个核心的索引 */ val coreStart: UInt, /** * Number of cores on this physical package + * 此物理封装上的核心数量 */ val coreCount: UInt, /** * Index of the first cluster of cores on this physical package + * 此物理封装上第一个核心集群的索引 */ val clusterStart: UInt, /** * Number of clusters of cores on this physical package + * 此物理封装上的核心集群数量 */ val clusterCount: UInt, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Processor.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Processor.kt index 754c42e..51e568a 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Processor.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Processor.kt @@ -13,45 +13,56 @@ import com.xyzshell.andinfo.libs.cpu.models.ProcessorCache /** * `struct cpuinfo_processor` + * 逻辑处理器信息结构体 */ data class Processor( /** * SMT (hyperthread) ID within a core + * 核心内的SMT（超线程）ID */ val smtId: UInt, /** * Core containing this logical processor + * 包含此逻辑处理器的核心 */ val core: Core, /** * Cluster of cores containing this logical processor + * 包含此逻辑处理器的核心集群 */ val cluster: Cluster, /** * Physical package containing this logical processor + * 包含此逻辑处理器的物理封装 */ val cpuPackage: Package, /** * Linux-specific ID for the logical processor: + * Linux特定的逻辑处理器ID： * - Linux kernel exposes information about this logical processor in + * - Linux内核在以下路径公开此逻辑处理器的信息 * /sys/devices/system/cpu/cpu/ * - Bit in the cpu_set_t identifies this logical processor + * - cpu_set_t中的位标识此逻辑处理器 */ val linuxId: UInt, /** * x86 only + * 仅x86架构 * * APIC ID (unique x86-specific ID of the logical processor) + * APIC ID（逻辑处理器的唯一x86特定ID） */ val apicId: UInt?, /** * @see ProcessorCache + * 处理器缓存信息 */ val cache: ProcessorCache, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/ProcessorCache.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/ProcessorCache.kt index 3ff358d..f2d3210 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/ProcessorCache.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/ProcessorCache.kt @@ -9,26 +9,32 @@ import com.xyzshell.andinfo.libs.cpu.models.Cache /** * `struct cpuinfo_processor { struct {...} cache }` + * 处理器缓存层次结构 */ data class ProcessorCache( /** * Level 1 instruction cache + * 一级指令缓存 */ val l1i: Cache?, /** * Level 1 data cache + * 一级数据缓存 */ val l1d: Cache?, /** * Level 2 unified or data cache + * 二级统一缓存或数据缓存 */ val l2: Cache?, /** * Level 3 unified or data cache + * 三级统一缓存或数据缓存 */ val l3: Cache?, /** * Level 4 unified or data cache + * 四级统一缓存或数据缓存 */ val l4: Cache?, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Tlb.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Tlb.kt index 162df42..3850064 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Tlb.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Tlb.kt @@ -7,10 +7,25 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `struct cpuinfo_tlb` + * TLB（Translation Lookaside Buffer）转换后备缓冲区结构体 */ data class Tlb( + /** + * TLB entries count + * TLB条目数量 + */ val entries: UInt, + + /** + * Associativity of the TLB + * TLB的关联度 + */ val associativity: UInt, + + /** + * Number of pages + * 页面数量 + */ val pages: ULong, ) { companion object { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/TraceCache.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/TraceCache.kt index 0d1ff72..95d3f4c 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/TraceCache.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/TraceCache.kt @@ -7,9 +7,19 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `struct cpuinfo_trace_cache` + * 跟踪缓存结构体（用于存储已解码的微操作） */ data class TraceCache( + /** + * Number of micro-operations + * 微操作数量 + */ val uops: UInt, + + /** + * Associativity of the trace cache + * 跟踪缓存的关联度 + */ val associativity: UInt, ) { companion object { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Uarch.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Uarch.kt index 5ac0e1f..e7b66c3 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Uarch.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Uarch.kt @@ -7,12 +7,15 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `enum cpuinfo_uarch` + * CPU微架构枚举 * * Processor microarchitecture + * 处理器微架构 * * Processors with different microarchitectures often have different instruction * performance characteristics, and may have dramatically different pipeline * organization. + * 不同微架构的处理器通常具有不同的指令性能特征，并且可能具有截然不同的流水线组织结构 */ enum class Uarch( val value: UInt, @@ -20,189 +23,227 @@ enum class Uarch( /** * Microarchitecture is unknown, or the library failed to get * information about the microarchitecture from OS + * 微架构未知，或库无法从操作系统获取微架构信息 */ UNKNOWN(0U), /** * Pentium and Pentium MMX microarchitecture. + * 奔腾和奔腾MMX微架构 */ P5(0x00100100U), /** * Intel Quark microarchitecture. + * 英特尔夸克微架构 */ QUARK(0x00100101U), /** * Pentium Pro, Pentium II, and Pentium III. + * 奔腾Pro、奔腾II和奔腾III */ P6(0x00100200U), /** * Pentium M. + * 奔腾M */ DOTHAN(0x00100201U), /** * Intel Core microarchitecture. + * 英特尔酷睿微架构 */ YONAH(0x00100202U), /** * Intel Core 2 microarchitecture on 65 nm process. + * 英特尔酷睿2微架构（65纳米工艺） */ CONROE(0x00100203U), /** * Intel Core 2 microarchitecture on 45 nm process. + * 英特尔酷睿2微架构（45纳米工艺） */ PENRYN(0x00100204U), /** * Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st * gen). + * 英特尔Nehalem和Westmere微架构（酷睿i3/i5/i7第1代） */ NEHALEM(0x00100205U), /** * Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). + * 英特尔Sandy Bridge微架构（酷睿i3/i5/i7第2代） */ SANDY_BRIDGE(0x00100206U), /** * Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). + * 英特尔Ivy Bridge微架构（酷睿i3/i5/i7第3代） */ IVY_BRIDGE(0x00100207U), /** * Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). + * 英特尔Haswell微架构（酷睿i3/i5/i7第4代） */ HASWELL(0x00100208U), /** * Intel Broadwell microarchitecture. + * 英特尔Broadwell微架构（第5代） */ BROADWELL(0x00100209U), /** * Intel Sky Lake microarchitecture (14 nm, including * Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). + * 英特尔Sky Lake微架构（14纳米，包括Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake） */ SKY_LAKE(0x0010020AU), /** * DEPRECATED (Intel Kaby Lake microarchitecture). + * 已弃用（英特尔Kaby Lake微架构） */ //KABY_LAKE(0x0010020AU), /** * Intel Palm Cove microarchitecture (10 nm, Cannon Lake). + * 英特尔Palm Cove微架构（10纳米，Cannon Lake） */ PALM_COVE(0x0010020BU), /** * Intel Sunny Cove microarchitecture (10 nm, Ice Lake). + * 英特尔Sunny Cove微架构（10纳米，Ice Lake） */ SUNNY_COVE(0x0010020CU), /** * Pentium 4 with Willamette, Northwood, or Foster cores. + * 奔腾4（Willamette、Northwood或Foster核心） */ WILLAMETTE(0x00100300U), /** * Pentium 4 with Prescott and later cores. + * 奔腾4（Prescott及更高版本核心） */ PRESCOTT(0x00100301U), /** * Intel Atom on 45 nm process. + * 英特尔凌动（45纳米工艺） */ BONNELL(0x00100400U), /** * Intel Atom on 32 nm process. + * 英特尔凌动（32纳米工艺） */ SALTWELL(0x00100401U), /** * Intel Silvermont microarchitecture (22 nm out-of-order Atom). + * 英特尔Silvermont微架构（22纳米乱序执行凌动） */ SILVERMOUNT(0x00100402U), /** * Intel Airmont microarchitecture (14 nm out-of-order Atom). + * 英特尔Airmont微架构（14纳米乱序执行凌动） */ AIRMONT(0x00100403U), /** * Intel Goldmont microarchitecture (Denverton, Apollo Lake). + * 英特尔Goldmont微架构（Denverton、Apollo Lake） */ GOLDMONT(0x00100404U), /** * Intel Goldmont Plus microarchitecture (Gemini Lake). + * 英特尔Goldmont Plus微架构（Gemini Lake） */ GOLDMONT_PLUS(0x00100405U), /** * Intel Knights Ferry HPC boards. + * 英特尔Knights Ferry高性能计算板 */ KNIGHTS_FERRY(0x00100500U), /** * Intel Knights Corner HPC boards (aka Xeon Phi). + * 英特尔Knights Corner高性能计算板（即至强融核） */ KNIGHTS_CORNER(0x00100501U), /** * Intel Knights Landing microarchitecture (second-gen MIC). + * 英特尔Knights Landing微架构（第二代MIC） */ KNIGHTS_LANDING(0x00100502U), /** * Intel Knights Hill microarchitecture (third-gen MIC). + * 英特尔Knights Hill微架构（第三代MIC） */ KNIGHTS_HILL(0x00100503U), /** * Intel Knights Mill Xeon Phi. + * 英特尔Knights Mill至强融核 */ KNIGHTS_MILL(0x00100504U), /** * Intel/Marvell XScale series. + * 英特尔/美满XScale系列 */ XSCALE(0x00100600U), /** * AMD K5. + * AMD K5微架构 */ K5(0x00200100U), /** * AMD K6 and alike. + * AMD K6及类似微架构 */ K6(0x00200101U), /** * AMD Athlon and Duron. + * AMD速龙和毒龙 */ K7(0x00200102U), /** * AMD Athlon 64, Opteron 64. + * AMD速龙64、皓龙64 */ K8(0x00200103U), /** * AMD Family 10h (Barcelona, Istambul, Magny-Cours). + * AMD Family 10h（Barcelona、Istambul、Magny-Cours） */ K10(0x00200104U), /** * AMD Bulldozer microarchitecture * Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs. + * AMD推土机微架构 + * Zambezi FX系列CPU、Zurich、Valencia和Interlagos皓龙CPU */ BULLDOZER(0x00200105U), @@ -210,242 +251,291 @@ enum class Uarch( * AMD Piledriver microarchitecture * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu * Dhabi Opteron CPUs. + * AMD打桩机微架构 + * Vishera FX系列CPU、Trinity和Richland APU、Delhi、Seoul、Abu Dhabi皓龙CPU */ PILEDRIVER(0x00200106U), /** * AMD Steamroller microarchitecture (Kaveri APUs). + * AMD压路机微架构（Kaveri APU） */ STEAMROLLER(0x00200107U), /** * AMD Excavator microarchitecture (Carizzo APUs). + * AMD挖掘机微架构（Carizzo APU） */ EXCAVATOR(0x00200108U), /** * AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). + * AMD Zen微架构（12/14纳米锐龙和霄龙CPU） */ ZEN(0x00200109U), /** * AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). + * AMD Zen 2微架构（7纳米锐龙和霄龙CPU） */ ZEN2(0x0020010AU), /** * AMD Zen 3 microarchitecture. + * AMD Zen 3微架构 */ ZEN3(0x0020010BU), /** * AMD Zen 4 microarchitecture. + * AMD Zen 4微架构 */ ZEN4(0x0020010CU), /** * NSC Geode and AMD Geode GX and LX. + * NSC Geode和AMD Geode GX和LX */ GEODE(0x00200200U), /** * AMD Bobcat mobile microarchitecture. + * AMD山猫移动微架构 */ BOBCAT(0x00200201U), /** * AMD Jaguar mobile microarchitecture. + * AMD美洲豹移动微架构 */ JAGUAR(0x00200202U), /** * AMD Puma mobile microarchitecture. + * AMD美洲狮移动微架构 */ PUMA(0x00200203U), /** * ARM7 series. + * ARM7系列 */ ARM7(0x00300100U), /** * ARM9 series. + * ARM9系列 */ ARM9(0x00300101U), /** * ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. + * ARM 1136、ARM 1156、ARM 1176或ARM 11MPCore */ ARM11(0x00300102U), /** * ARM Cortex-A5. + * ARM Cortex-A5 */ CORTEX_A5(0x00300205U), /** * ARM Cortex-A7. + * ARM Cortex-A7 */ CORTEX_A7(0x00300207U), /** * ARM Cortex-A8. + * ARM Cortex-A8 */ CORTEX_A8(0x00300208U), /** * ARM Cortex-A9. + * ARM Cortex-A9 */ CORTEX_A9(0x00300209U), /** * ARM Cortex-A12. + * ARM Cortex-A12 */ CORTEX_A12(0x00300212U), /** * ARM Cortex-A15. + * ARM Cortex-A15 */ CORTEX_A15(0x00300215U), /** * ARM Cortex-A17. + * ARM Cortex-A17 */ CORTEX_A17(0x00300217U), /** * ARM Cortex-A32. + * ARM Cortex-A32 */ CORTEX_A32(0x00300332U), /** * ARM Cortex-A35. + * ARM Cortex-A35 */ CORTEX_A35(0x00300335U), /** * ARM Cortex-A53. + * ARM Cortex-A53 */ CORTEX_A53(0x00300353U), /** * ARM Cortex-A55 revision 0 (restricted dual-issue capabilities * compared to revision 1+). + * ARM Cortex-A55修订版0（相比修订版1+，双发射能力受限） */ CORTEX_A55R0(0x00300354U), /** * ARM Cortex-A55. + * ARM Cortex-A55 */ CORTEX_A55(0x00300355U), /** * ARM Cortex-A57. + * ARM Cortex-A57 */ CORTEX_A57(0x00300357U), /** * ARM Cortex-A65. + * ARM Cortex-A65 */ CORTEX_A65(0x00300365U), /** * ARM Cortex-A72. + * ARM Cortex-A72 */ CORTEX_A72(0x00300372U), /** * ARM Cortex-A73. + * ARM Cortex-A73 */ CORTEX_A73(0x00300373U), /** * ARM Cortex-A75. + * ARM Cortex-A75 */ CORTEX_A75(0x00300375U), /** * ARM Cortex-A76. + * ARM Cortex-A76 */ CORTEX_A76(0x00300376U), /** * ARM Cortex-A77. + * ARM Cortex-A77 */ CORTEX_A77(0x00300377U), /** * ARM Cortex-A78. + * ARM Cortex-A78 */ CORTEX_A78(0x00300378U), /** * ARM Neoverse N1. + * ARM Neoverse N1（服务器级） */ NEOVERSE_N1(0x00300400U), /** * ARM Neoverse E1. + * ARM Neoverse E1（边缘计算级） */ NEOVERSE_E1(0x00300401U), /** * ARM Neoverse V1. + * ARM Neoverse V1（高性能级） */ NEOVERSE_V1(0x00300402U), /** * ARM Neoverse N2. + * ARM Neoverse N2 */ NEOVERSE_N2(0x00300403U), /** * ARM Neoverse V2. + * ARM Neoverse V2 */ NEOVERSE_V2(0x00300404U), /** * ARM Cortex-X1. + * ARM Cortex-X1（超大核） */ CORTEX_X1(0x00300501U), /** * ARM Cortex-X2. + * ARM Cortex-X2（超大核） */ CORTEX_X2(0x00300502U), /** * ARM Cortex-X3. + * ARM Cortex-X3（超大核） */ CORTEX_X3(0x00300503U), /** * ARM Cortex-X4. + * ARM Cortex-X4（超大核） */ CORTEX_X4(0x00300504U), /** * ARM Cortex-A510. + * ARM Cortex-A510（小核） */ CORTEX_A510(0x00300551U), /** * ARM Cortex-A520. + * ARM Cortex-A520（小核） */ CORTEX_A520(0x00300552U), /** * ARM Cortex-A710. + * ARM Cortex-A710（大核） */ CORTEX_A710(0x00300571U), /** * ARM Cortex-A715. + * ARM Cortex-A715（大核） */ CORTEX_A715(0x00300572U), /** * ARM Cortex-A720. + * ARM Cortex-A720（大核） */ CORTEX_A720(0x00300573U), diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/UarchInfo.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/UarchInfo.kt index 1b79eb3..6bfac3a 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/UarchInfo.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/UarchInfo.kt @@ -10,30 +10,36 @@ import com.xyzshell.andinfo.libs.cpu.models.Uarch /** * `struct cpuinfo_uarch_info` + * CPU微架构信息结构体 */ data class UarchInfo( /** * Type of CPU microarchitecture + * CPU微架构类型 */ val uarch: Uarch, /** * Value of CPUID leaf 1 EAX register for the microarchitecture + * 该微架构的CPUID leaf 1 EAX寄存器值（x86专用） */ val cpuid: UInt?, /** * Value of Main ID Register (MIDR) for the microarchitecture + * 该微架构的主ID寄存器（MIDR）值（ARM专用） */ val midr: Midr?, /** * Number of logical processors with the microarchitecture + * 使用此微架构的逻辑处理器数量 */ val processorCount: UInt, /** * Number of cores with the microarchitecture + * 使用此微架构的核心数量 */ val coreCount: UInt, ) { diff --git a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Vendor.kt b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Vendor.kt index df1a251..662eef9 100644 --- a/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Vendor.kt +++ b/myphoneinfo/andinfo/src/main/java/com/xyzshell/andinfo/libs/cpu/models/Vendor.kt @@ -7,8 +7,10 @@ package com.xyzshell.andinfo.libs.cpu.models /** * `enum cpuinfo_vendor` + * CPU供应商枚举 * * Vendor of processor core design + * 处理器核心设计的供应商 */ enum class Vendor( val value: UInt, @@ -16,207 +18,253 @@ enum class Vendor( /** * Processor vendor is not known to the library, or the library failed * to get vendor information from the OS. + * 处理器供应商未知，或库无法从操作系统获取供应商信息 */ UNKNOWN(0U), /** * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor * microarchitectures. + * 英特尔公司。x86、x86-64、IA64和ARM处理器微架构的供应商 * * Sold its ARM design subsidiary in 2006. The last ARM processor design * was released in 2004. + * 2006年出售了其ARM设计子公司。最后一款ARM处理器设计于2004年发布 */ INTEL(1U), /** * Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor * microarchitectures. + * 超威半导体公司（AMD）。x86和x86-64处理器微架构的供应商 */ AMD(2U), /** * ARM Holdings plc. Vendor of ARM and ARM64 processor * microarchitectures. + * ARM控股有限公司。ARM和ARM64处理器微架构的供应商 */ ARM(3U), /** * Qualcomm Incorporated. Vendor of ARM and ARM64 processor * microarchitectures. + * 高通公司。ARM和ARM64处理器微架构的供应商 */ QUALCOMM(4U), /** * Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. + * 苹果公司。ARM和ARM64处理器微架构的供应商 */ APPLE(5U), /** * Samsung Electronics Co., Ltd. Vendir if ARM64 processor * microarchitectures. + * 三星电子有限公司。ARM64处理器微架构的供应商 */ SAMSUNG(6U), /** * Nvidia Corporation. Vendor of ARM64-compatible processor * microarchitectures. + * 英伟达公司。ARM64兼容处理器微架构的供应商 */ NVIDIA(7U), /** * MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. + * MIPS科技公司。MIPS处理器微架构的供应商 */ MIPS(8U), /** * International Business Machines Corporation. Vendor of PowerPC * processor microarchitectures. + * 国际商业机器公司（IBM）。PowerPC处理器微架构的供应商 */ IBM(9U), /** * Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. + * 君正半导体。MIPS处理器微架构的供应商 */ INGENIC(10U), /** * VIA Technologies, Inc. Vendor of x86 and x86-64 processor * microarchitectures. + * 威盛科技股份有限公司。x86和x86-64处理器微架构的供应商 * * Processors are designed by Centaur Technology, a subsidiary of VIA * Technologies. + * 处理器由威盛科技的子公司Centaur Technology设计 */ VIA(11U), /** * Cavium, Inc. Vendor of ARM64 processor microarchitectures. + * Cavium公司。ARM64处理器微架构的供应商 */ CAVIUM(12U), /** * Broadcom, Inc. Vendor of ARM processor microarchitectures. + * 博通公司。ARM处理器微架构的供应商 */ BROADCOM(13U), /** * Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor * microarchitectures. + * 应用微电路公司（APM）。ARM64处理器微架构的供应商 */ APM(14U), /** * Huawei Technologies Co., Ltd. Vendor of ARM64 processor * microarchitectures. + * 华为技术有限公司。ARM64处理器微架构的供应商 * * Processors are designed by HiSilicon, a subsidiary of Huawei. + * 处理器由华为的子公司海思半导体设计 */ HUAWEI(15U), /** * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor * of x86-64 processor microarchitectures. + * 海光（成都海光集成电路设计有限公司）。x86-64处理器微架构的供应商 * * Processors are variants of AMD cores. + * 处理器是AMD核心的变体 */ HYGON(16U), /** * SiFive, Inc. Vendor of RISC-V processor microarchitectures. + * SiFive公司。RISC-V处理器微架构的供应商 */ SIFIVE(17U), /** * Texas Instruments Inc. Vendor of ARM processor microarchitectures. + * 德州仪器公司。ARM处理器微架构的供应商 */ TEXAS_INSTRUMENTS(30U), /** * Marvell Technology Group Ltd. Vendor of ARM processor * microarchitectures. + * 美满电子科技集团。ARM处理器微架构的供应商 */ MARVELL(31U), /** * RDC Semiconductor Co., Ltd. Vendor of x86 processor * microarchitectures. + * 扬智科技股份有限公司。x86处理器微架构的供应商 */ RDC(32U), /** * DM&P Electronics Inc. Vendor of x86 processor microarchitectures. + * 帝睿电子公司。x86处理器微架构的供应商 */ DMP(33U), /** * Motorola, Inc. Vendor of PowerPC and ARM processor * microarchitectures. + * 摩托罗拉公司。PowerPC和ARM处理器微架构的供应商 */ MOTOROLA(34U), /** * Transmeta Corporation. Vendor of x86 processor microarchitectures. + * 全美达公司。x86处理器微架构的供应商 * * Now defunct. The last processor design was released in 2004. * Transmeta processors implemented VLIW ISA and used binary translation * to execute x86 code. + * 现已倒闭。最后一款处理器设计于2004年发布。全美达处理器实现了VLIW指令集， + * 并使用二进制翻译来执行x86代码 */ TRANSMETA(50U), /** * Cyrix Corporation. Vendor of x86 processor microarchitectures. + * Cyrix公司。x86处理器微架构的供应商 * * Now defunct. The last processor design was released in 1996. + * 现已倒闭。最后一款处理器设计于1996年发布 */ CYRIX(51U), /** * Rise Technology. Vendor of x86 processor microarchitectures. + * Rise科技。x86处理器微架构的供应商 * * Now defunct. The last processor design was released in 1999. + * 现已倒闭。最后一款处理器设计于1999年发布 */ RISE(52U), /** * National Semiconductor. Vendor of x86 processor microarchitectures. + * 美国国家半导体公司。x86处理器微架构的供应商 * * Sold its x86 design subsidiary in 1999. The last processor design was * released in 1998. + * 1999年出售了其x86设计子公司。最后一款处理器设计于1998年发布 */ NSC(53U), /** * Silicon Integrated Systems. Vendor of x86 processor * microarchitectures. + * 矽统科技。x86处理器微架构的供应商 * * Sold its x86 design subsidiary in 2001. The last processor design was * released in 2001. + * 2001年出售了其x86设计子公司。最后一款处理器设计于2001年发布 */ SIS(54U), /** * NexGen. Vendor of x86 processor microarchitectures. + * NexGen公司。x86处理器微架构的供应商 * * Now defunct. The last processor design was released in 1994. * NexGen designed the first x86 microarchitecture which decomposed x86 * instructions into simple microoperations. + * 现已倒闭。最后一款处理器设计于1994年发布。NexGen设计了第一个将x86 + * 指令分解为简单微操作的x86微架构 */ NEXGEN(55U), /** * United Microelectronics Corporation. Vendor of x86 processor * microarchitectures. + * 联华电子公司。x86处理器微架构的供应商 * * Ceased x86 in the early 1990s. The last processor design was released * in 1991. Designed U5C and U5D processors. Both are 486 level. + * 在1990年代初停止x86业务。最后一款处理器设计于1991年发布。设计了U5C + * 和U5D处理器，均为486级别 */ UMC(56U), /** * Digital Equipment Corporation. Vendor of ARM processor * microarchitecture. + * 迪吉多公司（DEC）。ARM处理器微架构的供应商 * * Sold its ARM designs in 1997. The last processor design was released * in 1997. + * 1997年出售了其ARM设计。最后一款处理器设计于1997年发布 */ DEC(57U);